高速铁路铁轨应力检测装置

High-speed railway stress testing device

Abstract

本发明提供了一种高速铁路铁轨应力检测装置,包括:MCU、第一FPGA处理电路、超声波发送探头以及至少两个超声波接收探头;MCU用于向超声波发送探头发送控制指令;超声波发送探头用于根据控制指令向高速铁路铁轨发送超声波信号;两个超声波接收探头分别用于接收不同时刻的超声波信号并将超声波信号发送至第一FPGA处理电路;第一FPGA处理电路用于接收超声波信号并计算两次超声波信号的接收时差,并根据接收时差确定高速铁路铁轨的绝对应力值,其通过FPGA中的比频比相等相关性算法分析计算接收的超声波信号的时差,并将该时差与标准应力延时样本值表进行比对,得到对应的铁轨绝对应力值和应力变化值,使得测量结果准确。
The invention provides a high-speed railway stress testing device. The device comprises a micro-programmed control unit (MCU), a first field programmable gate array (FPGA) processing circuit, an ultrasonic probe and send at least two ultrasonic receiving probe; MCU is used to send control commands sent to the ultrasonic probe; ultrasonic probe for transmitting an ultrasonic signal is sent to the high-speed railway tracks according to the control command; two ultrasonic receivers probes were different times for receiving the ultrasonic signal and an ultrasonic signal is transmitted to the first FPGA processing circuit; a first FPGA processing circuit for receiving an ultrasonic signal and receiving two ultrasonic signals to calculate the time difference, and determining the time difference from the received high-speed railway tracks the absolute stress values, its frequency ultrasonic signal ratio is equal to the time difference correlation analysis and calculation algorithm received by the FPGA ratio, and the time difference with the standard stress delay sample value table for comparison, to obtain the corresponding absolute stress value and rails stress values so that the measurement results are accurate.

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